`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:18:16 07/07/2014
// Design Name:   addr_mapping
// Module Name:   E:/Xilinx/Examples/powerpc_bsb_system/pcores/ppc440mc_ddr2_v3_00_c/hdl/verilog/testbench.v
// Project Name:  address_mapping
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: addr_mapping
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module testbench;

	// Inputs
	reg clk;
	reg reset;
	reg mi_mcaddressvalid;
	reg [0:35] mi_mcaddress;
	reg mi_mcbankconflict;
	reg mi_mcrowconflict;
	reg [0:15] mi_mcbyteenable;
	reg [0:127] mi_mcwritedata;
	reg mi_mcreadnotwrite;
	reg mi_mcwritedatavalid;
	reg _mc_miaddrreadytoaccept;
	reg [0:127] _mc_mireaddata;
	reg _mc_mireaddataerr;
	reg _mc_mireaddatavalid;

	// Outputs
	wire mc_miaddrreadytoaccept;
	wire [0:127] mc_mireaddata;
	wire mc_mireaddataerr;
	wire mc_mireaddatavalid;
	wire _mi_mcaddressvalid;
	wire [0:35] _mi_mcaddress;
	wire _mi_mcbankconflict;
	wire _mi_mcrowconflict;
	wire [0:15] _mi_mcbyteenable;
	wire [0:127] _mi_mcwritedata;
	wire _mi_mcreadnotwrite;
	wire _mi_mcwritedatavalid;

	// Instantiate the Unit Under Test (UUT)
	addr_mapping uut (
		.clk(clk), 
		.reset(reset), 
		.mi_mcaddressvalid(mi_mcaddressvalid), 
		.mi_mcaddress(mi_mcaddress), 
		.mi_mcbankconflict(mi_mcbankconflict), 
		.mi_mcrowconflict(mi_mcrowconflict), 
		.mi_mcbyteenable(mi_mcbyteenable), 
		.mi_mcwritedata(mi_mcwritedata), 
		.mi_mcreadnotwrite(mi_mcreadnotwrite), 
		.mi_mcwritedatavalid(mi_mcwritedatavalid), 
		.mc_miaddrreadytoaccept(mc_miaddrreadytoaccept), 
		.mc_mireaddata(mc_mireaddata), 
		.mc_mireaddataerr(mc_mireaddataerr), 
		.mc_mireaddatavalid(mc_mireaddatavalid), 
		._mi_mcaddressvalid(_mi_mcaddressvalid), 
		._mi_mcaddress(_mi_mcaddress), 
		._mi_mcbankconflict(_mi_mcbankconflict), 
		._mi_mcrowconflict(_mi_mcrowconflict), 
		._mi_mcbyteenable(_mi_mcbyteenable), 
		._mi_mcwritedata(_mi_mcwritedata), 
		._mi_mcreadnotwrite(_mi_mcreadnotwrite), 
		._mi_mcwritedatavalid(_mi_mcwritedatavalid), 
		._mc_miaddrreadytoaccept(_mc_miaddrreadytoaccept), 
		._mc_mireaddata(_mc_mireaddata), 
		._mc_mireaddataerr(_mc_mireaddataerr), 
		._mc_mireaddatavalid(_mc_mireaddatavalid)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		mi_mcaddressvalid = 0;
		mi_mcaddress = 0;
		mi_mcbankconflict = 0;
		mi_mcrowconflict = 0;
		mi_mcbyteenable = 0;
		mi_mcwritedata = 0;
		mi_mcreadnotwrite = 0;
		mi_mcwritedatavalid = 0;
		_mc_miaddrreadytoaccept = 0;
		_mc_mireaddata = 0;
		_mc_mireaddataerr = 0;
		_mc_mireaddatavalid = 0;

		// Wait 100 ns for global reset to finish
	end
	
	always
		#5 clk = !clk;
	
	initial begin
		#10 reset = 1;
		#20 reset = 0;
	end
	
	integer i;
	initial begin
		#30
		#5
		for (i = 0; i < 1024*1024; i = i + 1)
		begin 
		@(posedge clk)
			mi_mcaddress = i;
		   mi_mcaddressvalid = 1;
		@(posedge clk)
			mi_mcaddressvalid = 0;
		end

	end
      
endmodule

